Normally-off heterojunction integrated device and method for manufacturing an integrated device

An integrated power device includes a heterostructure (10), having a channel layer (2) and a barrier layer (3), a source contact (7), a drain contact (8), a gate region (5) and a gate contact (9) on the gate region (5). An insulating gate structure (15)has a first insulating gate portion (15a) and a second insulating gate portion (15b), which extend in a conformable way along sides (5a, 9a) of the gate region (5) and of the gate contact (9) that face the drain contact (8). An insulating field structure (13), having a first dielectric region (13a) on the barrier layer (3) and a second dielectric region (13b) selectively etchable with respect to the first dielectric region (13a), is arranged on the barrier layer (3) between the gate region (5) and the drain contact. A source field plate (12) extends over the insulating field structure (13). On a side of the insulating field structure (13) towards the gate region (5), the source field plate (12) is in contact with the first dielectric region (13a). The source field plate is in contact with the second insulating gate portion (15b; 115b; 215b) along the sides (5a, 9a).