On the Voltage Stress Reduction in Hairpin Windings: Guidelines and Critical Aspects

Transportation electrification roadmaps are pushing for a step-change increase in power densities of electric drives, leading to rapidly growing developments of high-switching frequency wide bandgap (WBG) semiconductor-based inverters. Meanwhile, induced high dV/dt can challenge the reliability of the stator winding insulation system. This study provides guidelines to mitigate the winding voltage stress through the implementation of an improved modular hairpin winding (HW) layout featuring a multibranch design, reconfigurable by simply reconnecting phase terminals and neutral points. This enables comparison of voltage distributions across different winding layout patterns. A high-frequency electrical lumped parameter network for the prediction of voltage stress distribution is further adopted, and validated through experimental tests carried out on different configurations. The downselected configuration reduces by 35% the maximum interturn voltage. Furthermore, sensitivity analyses at different rise times revealed that improvement could be limited to only 10%–15% when rise times are in the range of tens of nanoseconds. Under these conditions, the first series turns connected to the inverter side are very sensitive to sudden voltage spikes and experience the highest voltage stress, even though they have fewer connecting conductors between them and adjacent layers. In general, the article provides reliability-oriented HW design guidelines that address the integrity of the insulation system.